Verilog Primer.pdf
This manual is primarily intended for students designing and testing VLSI integrated circuits or parts thereof at the VLSI laboratory of the DED (V2-324) using the CADENCE Verilog simulator environment on Sun workstations under the UNIX Operating System.
HDL Design with Precision RTL Synthesis: CPLD Flow Tutorial.pdf
Contents: Learning Objectives ~ Time to Complete This Tutorial ~ System Requirements ~ Accessing Online Help ~ About the Tutorial Design ~ About the Tutorial Data Flow ~ Task 1: Create a New Project ~ Task 2: Target a Device ~ Task 3: Create a Precision RTL Synthesis Project ~ Task 4: Add the Verilog HDL Source File ~ Task 5: Set Implementation Options ~ Task 6: Compile the Design ~ Task 7: Synthesize the Design ~ Task 8: Import the EDIF File into Your Project ~ Task 9: Fit the Design and View the Report ~ Task 10: Perform Static Timing Analysis ~ Summary ~ Glossary ~ Recommended Reference Materials
Precision RTL Synthesis Users Manual.pdf
Precision RTL Synthesis is a synthesis platform the maximizes the performance of both existing programmable logic devices (CPLDs and FPGAs) and next-generation, multi-million gate field programmable system-on-chip (FPSoC) devices. Precision RTL Synthesis is a comprehensive tool suite, providing design capture in the form of VHDL and Verilog entry, advanced register- transfer-level logic synthesis, constraint-based optimization, state-of-the-art timing analysis, schematic viewing and encapsulated place-and-route. Precision RTL Synthesis runs on PC platforms using Windows 2000/NT/XP and Linux RedHat; and UNIX Sun and HP platforms. Refer to the Precision Synthesis Installation Guide for detailed information about supported system configurations and requirements.
Precision RTL Synthesis Style Guide.pdf
Before you use Precision Synthesis to perform RTL synthesis on your design, you should already have a good understanding of the syntax and semantics of VHDL and /or Verilog. This manual describes how Precision RTL Synthesis views these two HDL languages and makes recommendations on the style to use to achieve the best synthesized design.
You might also be interested in reading:verilog, Verilog Styles for Synthesis of Digital Systems, System Verilog ebook, free complete verilog ebooks, verilog styles for synthesis of digital systems ebook
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