s p o n s o r e d   l i n k s

verilog primer

Verilog Primer.pdf

August 10, 2008 · Filed Under Electrical Engineering · 1 Comment  · Tags: , ,

This manual is primarily intended for students designing and testing VLSI integrated circuits or parts thereof at the VLSI laboratory of the DED (V2-324) using the CADENCE Verilog simulator environment on Sun workstations under the UNIX Operating System.

s p o n s o r e d   l i n k s