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HDL Design with Precision RTL Synthesis: CPLD Flow Tutorial.pdf

July 13, 2008 · Filed Under Electrical Engineering · 1 Comment  · Tags: , ,

Contents: Learning Objectives ~ Time to Complete This Tutorial ~ System Requirements ~ Accessing Online Help ~ About the Tutorial Design ~ About the Tutorial Data Flow ~ Task 1: Create a New Project ~ Task 2: Target a Device ~ Task 3: Create a Precision RTL Synthesis Project ~ Task 4: Add the Verilog HDL Source File ~ Task 5: Set Implementation Options ~ Task 6: Compile the Design ~ Task 7: Synthesize the Design ~ Task 8: Import the EDIF File into Your Project ~ Task 9: Fit the Design and View the Report ~ Task 10: Perform Static Timing Analysis ~ Summary ~ Glossary ~ Recommended Reference Materials

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