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VHDL Modelling Guidelines.pdf

July 7, 2008 · Filed Under Electrical Engineering  · Tags: ,

This document defines requirements on VHDL models and testbenches, and is intended to be used as an applicable document for ESA developments involving VHDL modelling. It is mainly focused on digital models; specific requirements for analog modelling have not been covered.

Contents:

  • INTRODUCTION [ Purpose and scope ~ Applicable Documents ~ Reference Documents ]
  • REQUIREMENTS FOR ALL KINDS OF MODELS [ General ~ Names ~ Comments ~ Types ~ Files ~ Signals and ports ~ Assertions ~ Subprograms, processes, entities, architectures, component declarations ~ Configurations ~ Packages ~ Design libraries ~ Constructs to be avoided ~ Verification ~ Format of deliverable items ]
  • ADDITIONAL REQUIREMENTS [ Models for Component simulation ~ Names ~ Types ~ Model interface ~ Models for Board-level simulation ~ Names ~ Model interface ~ Handling of unknown values ~ Timing ~ Verification ~ Models for System-level simulation ~ Model interface ~ Verification ~ Testbenches ~ Automated verification ]

This is available FREE at RASSP Support Page for VHDL website, we merely collect the information, we are neither affiliated with the author(s), the website and any brand nor responsible for its content and change of content. (Read our disclaimer here or here before you download the document from the website written above by clicking the below link).

Download free VHDL Modelling Guidelines.pdf (50 pages pdf file, 0.1 MB).

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Comments

One Response to “VHDL Modelling Guidelines.pdf”

  1. arun on July 12th, 2008 4:26 pm

    good

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