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Precision RTL Synthesis Users Manual.pdf

July 4, 2008 · Filed Under Electrical Engineering  · Tags: , , , ,

Precision RTL Synthesis is a comprehensive tool suite, providing design capture in the form of VHDL and Verilog entry, advanced register- transfer-level logic synthesis, constraint-based optimization, state-of-the-art timing analysis, schematic viewing and encapsulated place-and-route. This manual describes the synthesis design process using the Precision RTL Synthesis Graphical User Interface (GUI) and provides information on how to perform synthesis tasks and analysis procedures.

Contents:

  • Chapter 1 [ Introducing Precision RTL Synthesis ~ Precision RTL Synthesis Features ~ Intuitive User Interface ~ Project Manager ~ Advanced Synthesis Algorithms ~ Constraint Driven Synthesis ~ Boundaryless Optimization ~ FSM Optimization ~ PreciseTimeTM Timing Analysis ~ Interactive Timing Analysis ~ Register Retiming ~ Schematic Viewing with Critical Path Fragment Filtering ~ Integrated Creation and Analysis Tools ~ Design Bar ~ HDLInventor ~ Project Browser ~ Design Browser ~ Schematic Viewing ~ P&RIntegrator ~ Documentation Available Online ~ Context-Sensitive Help ~ Product Manuals ]
  • Chapter 2 [ Setting Up a Design and Compiling ~ Invoking Precision RTL Synthesis ~ Invoking the Precision GUI ~ Invoking Precision from a Shell ~ Setting up the Design Environment ~ The Project Directory and the Results Directory. ~ Setting the Input Directory ~ Setting the Technology ~ Adding Input Files to the Project ~ Setting Synthesis Options ~ Compiling the Design ~ Evaluating the Results ~ Setting Timing and Design Constraints ~ Synthesizing the Design ~ Evaluating the Results ~ Performing Initial Place and Route ]
  • Chapter 3 [ Setting Constraints and Synthesizing ~ Managing a Master Constraint File ~ Creating a Master Constraint File ~ Maintaining a Master Constraint File ~ Setting Timing Constraints ~ Setting Global Timing Constraints ~ Clocks Overview ~ Derived Clocks ~ Report Timing and Clock Names ~ Specifying Clock Constraints ~ Handling Multiple Clocks ~ Specifying Input Delay ~ Specifying Output Delay ~ Setting False Paths ~ Setting Multicycle Paths ~ Setting Mapping Constraints ~ Mapping Ports to Pin Numbers and IO Pads ~ Mapping Operators, Counters, and Memory to Chip Resources ~ Setting Other Constraints ~ Controlling Hierarchy ~ Protecting Blocks from Change (dont_touch) ~ Controlling Fanout on Data Nets ]
  • Chapter 4 [ Managing Projects ~ The Project Manager ~ Bypassing the Project Manager ~ Using the Project Manager Interactively ~ Creating a Project. ~ Opening a Project. ~ Closing a Project ~ Setting Up the Implementation ~ Creating a New Implementation ~ Creating an Implementation from the Command Line ~ Saving the Active Implementation ~ Renaming an Implementation ~ Activating an Implementation ~ Copying an Implementation. ~ Commenting an Implementation ~ Deleting an Implementation. ~ Creating a Script from a Precision.log File ~ Scripts for Creating New Projects or Reusing Existing Projects ~ Exporting your Settings ~ Actions to Take if the Project, Input Directory, or Input Files Move ~ Backward Compatibility with Pre-2003c Projects ]
  • Chapter 5 [ Viewing a Schematic ~ A Quick Way to Bring Up a Schematic ~ Viewing the RTL Schematic ~ Viewing the Technology Schematic ~ Viewing the Critical Path Schematic ~ Understanding the Left Mouse Button Actions ~ Traversing the Schematic with Strokes ~ Zooming to Area ~ Zooming Out ~ Zooming In ~ Zooming to Fit ~ Moving Up and Down the Hierarchy ~ Paging Forward ( ) and Paging Back ( ) ~ Tracing a Signal to the Next Page ~ Panning the Schematic. ~ Centering an Object in the Schematic View ~ Viewing the Internals of a Hierarchy Block ~ Traversing the Schematic Using Keyboard shortcuts. ~ Using the Cross Probe Features ~ Cross Probing from Schematic to the HDL Source ~ Cross Probing to HDL Designer from Precision RTL Synthesis ~ Viewing Schematic Fragments ~ Tracing a Signal ~ Viewing a Trace Schematic ~ Click and Sprout the Trace Path ~ Using the Find Window Features ~ Conducting a Simple Search for Objects ~ Searching for Objects Using Regular Expressions ~ Setting Schematic Viewing Options ~ Understanding the Term "Bused Instance" ~ Viewing Bundled Instances and Net Buses ~ Changing the Schematic Printing Defaults ~ Changing the Way Symbols are Handled ~ Changing the Placement of Output Devices ~ Changing the Viewer Display and Color Options ]

This guide is available FREE at Dept. of Electrical and Computer Engineering University of Illinois website, we merely collect the information, we are neither affiliated with the author(s), the website and any brand nor responsible for its content and change of content. (Read our disclaimer here or here before you download the document from the website written above by clicking the below link).

Download Free: Precision RTL Synthesis Users Manual.pdf (119 pages pdf file, 2.2 MB).

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