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Precision RTL Synthesis Style Guide.pdf

July 4, 2008 · Filed Under Electrical Engineering  · Tags: , , , ,

VHDL is a high level description language for system and circuit design. The language supports various levels of abstraction. In contrast to regular netlist formats that supports only structural description and a boolean entry system that supports only dataflow behavior, VHDL supports a wide range of description styles. These include structural descriptions, dataflow descriptions and behavioral descriptions.

The structural and dataflow descriptions show a concurrent behavior. That is, all statements are executed concurrently, and the order of the statements is not relevant. On the other hand, behavioral descriptions are executed sequentially in processes, procedures and functions in VHDL. The behavioral descriptions resemble high-level programming languages.

VHDL allows a mixture of various levels of design entry abstraction. Precision RTL Synthesis Synthesizes will accept all levels of abstraction, and minimize the amount of logic needed…

Contents:

  • Chapter 1 [ Introduction to VHDL Synthesis ~ Overview. ~ VHDL and Synthesis ]
  • Chapter 2 [ VHDL Language Features ~ Entities and Architectures ~ Configuration ~ Processes ~ Literals ~ Types ~ Enumerated Types ~ Integer Types ~ Floating-point Types ~ Physical Types ~ Syntax and Semantics ~ Array Types ~ Record Types ~ Subtypes. ~ Type Conversions ~ IEEE 1076 Predefined Types ~ IEEE 1164 Predefined Types ~ Objects ~ Signals ~ Constants ~ Variables ~ Ports ~ Generics ~ Loop Variables. ~ Statements ~ Conditional Statements ~ Selection Statements ~ Loop Statements and Generate Statements. ~ Assignment Statements. ~ Operators ~ IEEE 1076 Predefined Operators. ~ IEEE 1164 Predefined Operators. ~ Operator Overloading ~ Attributes ~ VHDL Predefined Attributes ~ Mentor Graphics Predefined Attributes ~ User-Defined Attributes ~ Using Attributes in the Source Code ~ Blocks ~ Functions And Procedures ~ Resolution Functions ~ Syntax and Semantics ~ Synthesis Issues ~ Component Instantiation ~ Binding a Component ~ Option 1 - Using a Default Binding. ~ Option 2 - Using a Configuration Specification ~ Option 3 - Matching a Component Name to a Library ~ Option 4 - Creating a Black Box by Omitting the Entity ~ Packages. ~ Aliases ]
  • Chapter 3 [ The Art of VHDL Synthesis ~ Registers, Latches and Resets ~ Level-Sensitive Latch ~ Edge-Sensitive Flip-Flops. ~ Wait Statements ~ Variables ~ Predefined Flip-flops and Latches ~ Assigning I/O Buffers From VHDL ~ Buffer Assignment Using Component Instantiation ~ Three-state Buffers ~ Bidirectional Buffers ~ Buses ~ State Machines ~ General State Machine Description ~ VHDL Coding Style For State Machines ~ Power-up And Reset ~ Encoding Methods ~ Arithmetic And Relational Logic ~ Resource Sharing ~ Ranged Integers ~ Advanced Design Optimization. ~ Technology-Specific Macros ~ Multiplexers and Selectors. ~ ROMs, PLAs And Decoders ]
  • Chapter 4 [ The VHDL Environment ~ Entity and Package Handling ~ Entity Compiled as the Design Root ~ Finding Definitions of Components ~ How to Use Packages ~ Interfacing With Other VHDL Tools ~ VHDL Simulators ~ Synopsys ~ The exemplar Packages ~ Predefined Types ~ Predefined Attributes ~ Predefined Functions ~ Predefined Procedures ~ Syntax and Semantic Restrictions. ~ Synthesis Tool Restrictions ~ VHDL Language Restrictions ]
  • Chapter 5 [ Introduction to Verilog Synthesis ~ Verilog and Synthesis ~ Verilog 2001 Support ~ Introduction. ~ Supported Verilog 2001 Constructs. ~ Detailed Description ]
  • Chapter 6 [ Verilog Language Features. ~ Modules ~ 'macromodule'. ~ Numbers ~ Data Types ~ Net Data Types ~ Register Data Type ~ Parameter Data Type ~ Continuous Assignments ~ Net Declaration Assignment ~ Continuous Assignment Statement ~ Procedural Assignments ~ Always Blocks ~ Module Instantiation ~ Parameter Override During Instantiation of Module ~ Defparam Statement ~ 'unconnected_drive' and 'nounconnected_drive' ~ Operators ~ Operands ~ 'signed and 'unsigned Attributes on Operators ~ Operator Precedence ~ Statements ~ If-Else Statements ~ Case Statements ~ Case Statement and Multiplexer Generation ~ for Statements ~ Disable Statement ~ forever, repeat, while and Generalized Form of for ~ Functions and Tasks ~ Functions ~ Tasks ~ Inout Ports in Task ~ Access of Global Variables from Functions and ~ System Task Calls. ~ System Function Calls ~ Initial Statement ~ Compiler Directives ]
  • Chapter 7 [ The Art of Verilog Synthesis ~ Registers, Latches, and Resets ~ Level-Sensitive Latch ~ Edge-Sensitive Flip-flops ~ Assigning I/O Buffers from Verilog. ~ Buffer Assignment Using Component Instantiation ~ Tristate Buffers ~ Bidirectional Buffers. ~ Buses ~ State Machines ~ Moore Machines ~ Mealy Machines. ~ Issues in State Machine Design ~ Arithmetic and Relational Logic ~ Resource Sharing and Common Subexpression Elimination ~ Comparator Design ~ Technology-Specific Macros ~ Synthesis Directives ~ parallel_case and full_case directives ~ translate_off and translate_on directives ~ attribute directive ]
  • Chapter 8 [ Verilog and Synthesis of Logic. ~ Comparing With X and Z ~ Variable Indexing of Bit Vectors ~ Syntax and Semantic Restrictions ~ Unsupported Verilog Features ]
  • Chapter 9 [ Operators, Counters, and Memory ~ Inferring Operators ~ Inferring a Pipelined Multiplier ~ Mapping Operators to Dedicated Resources ~ Inferring Counters ~ Inferring Memory ~ How Memory Inferencing Works ~ Initializing a RAM in Verilog ~ Inferring ROM from the HDL Source Code. ]
  • Chapter 10 [ State Machine Synthesis ~ FSM Encoding Styles ~ FSM Encoding using VHDL Attributes ~ FSM Encoding using a Verilog Pragma ~ Advanced FSM Optimization ~ Safe State Machines ~ How Precision Implements a Safe FSM ]

Download free: Precision RTL Synthesis Style Guide.pdf (223 pages pdf file, 3.5 MB).

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