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Intel StrongARM SA-1110 Microprocessor Developer’s Manual.pdf

February 15, 2009 · Filed Under Electrical Engineering  · Tags: , , ,

The Intel StrongARM* SA-1110 Microprocessor (SA-1110) is a highly integrated communications microcontroller that incorporates a 32-bit StrongARM RISC processor core, system support logic, multiple communication channels, an LCD controller, a memory and PCMCIA controller, and general-purpose I/O ports.As do the Intel StrongARM SA-110 Microprocessor (SA-110) and Intel StrongARM SA-1100 Microprocessor (SA-1100), earlier members of the StrongARM family, the SA-1110 provides power efficiency, low cost, and high performance. Figure 1-1 shows the features of the SA-1110. The shaded boxes are features that have carried over with few or no changes from the SA-110. The nonshaded boxes are new or updated features for the SA-1110; most of the features are equivalent to that of the SA-1100. The SA-1110 differs from the SA-1100 only in the features of its memory and PCMCIA controller.

Contents:

  • Introduction 1
    • 1.1 Intel StrongARM SA-1110 Microprocessor
    • 1.2 Overview
    • 1.3 Example System
    • 1.4 ARM Architecture
  • Functional Description 2
    • 2.1 Block Diagram
    • 2.2 Inputs/Outputs
    • 2.3 Signal Description
    • 2.4 Memory Map
  • ARM Implementation Options 3
    • 3.1 Big and Little Endian
    • 3.2 Exceptions
    • 3.3 Coprocessors
  • Instruction Set 4
    • 4.1 Instruction Set
    • 4.2 Instruction Timing
  • Coprocessors 5
    • 5.1 Internal Coprocessor Instructions
    • 5.2 Coprocessor 15 Definition
  • Caches, Write Buffer, and Read Buffer 6
    • 6.1 Instruction Cache (Icache)
    • 6.2 Data Caches (Dcaches)
    • 6.3 Write Buffer (WB)
    • 6.4 Read Buffer (RB)
  • Memory Management Unit (MMU) 7
    • 7.1 Overview
    • 7.2 MMU Faults and CPU Aborts
    • 7.3 Data Aborts
    • 7.4 Interaction of the MMU, Icache, Dcache, and Write Buffer
    • 7.5 Mini Data Cache
  • Clocks 8
    • 8.1 Intel StrongARM SA-1110 Crystal Oscillators
    • 8.2 Core Clock Configuration Register
    • 8.2.1 Restrictions on Changing the Core Clock Configuration
    • 8.3 Driving Intel StrongARM SA-1110 Crystal Pins from an External Source
    • 8.4 Clocking During Test
  • System Control Module 9
    • 9.1 General-Purpose I/O
    • 9.2 Interrupt Controller
    • 9.3 Real-Time Clock
    • 9.4 Operating System Timer
    • 9.5 Power Manager
    • 9.6 Reset Controller
  • Memory and PCMCIA Control Module 10
    • 10.1 Overview of Operation
    • 10.2 Memory Configuration Registers
    • 10.3 SMROM Configuration Register (SMCNFG)
    • 10.4 Dynamic Interface Operation
    • 10.5 Static Memory Interface
    • 10.6 PCMCIA Overview
    • 10.7 Memory Interface Reset and Initialization
    • 10.8 Alternate Memory Bus Master Mode
  • Peripheral Control Module 11
    • 11.1 Read/Write Interface
    • 11.2 Memory Organization
    • 11.3 Interrupts
    • 11.4 Peripheral Pins
    • 11.5 Use of the GPIO Pins for Alternate Functions
    • 11.6 DMA Controller
    • 11.7 LCD Controller
    • 11.8 Serial Port 0 – USB Device Controller
    • 11.9 Serial Port 1 – GPCLK/UART
    • 11.10 Serial Port 2 – Infrared Communications Port (ICP)
    • 11.11 Serial Port 3 – UART
    • 11.12 Serial Port 4 – MCP / SSP
    • 11.13 Peripheral Pin Controller (PPC)
  • DC Parameters 12
    • 12.1 Absolute Maximum Ratings
    • 12.2 DC Operating Conditions
    • 12.3 Power Supply Voltages and Currents
  • AC Parameters 13
    • 13.1 Test Conditions
    • 13.2 Model Considerations
    • 13.3 Memory Bus and PCMCIA Signal Timings
    • 13.4 LCD Controller Signals
    • 13.5 MCP Signals
    • 13.6 Timing Parameters
    • 13.6.1 Asynchronous Signal Timing Descriptions
  • Package and Pinout 14
  • Debug Support 15
    • 15.1 Instruction Breakpoint
    • 15.2 Data Breakpoint
  • Boundary-Scan Test Interface 16
    • 16.1 Overview
    • 16.2 Reset
    • 16.3 Pull-Up Resistors
    • 16.4 Instruction Register
    • 16.5 Public Instructions
    • 16.6 Test Data Registers
    • 16.7 Boundary-Scan Interface Signals
  • Register Summary A
  • 3.6864–MHz Oscillator Specifications B
  • 32.768–KHz Oscillator Specifications C
  • Internal Test D

This manual is available FREE at Mike Channon’s website, we merely collect the information, we are neither affiliated with the author(s), the website and Intel brand nor responsible for its content and change of content. (Read our disclaimer here or here before you download the document from the website written above by clicking the below link).

Download free Intel StrongARM SA-1110 Microprocessor Developer’s Manual.pdf (406 pages pdf file, MB).

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